The present invention relates to a semiconductor integrated circuit, and more particularly to a master-slave flip-flop circuit.
In recent years, an LCD driver capable of operating at a high speed is demanded as liquid-crystal panel displays exhibit improved motion picture response. The speed of the LCD driver can be increased, for instance, by shortening the propagation delay time tpd of a flip-flop circuit (hereinafter referred to as the FF circuit) used in the LCD driver. It is also demanded that the FF circuit of a video signal input stage operate at an increased speed as an input video signal for the LCD driver is serialized. Consequently, it is demanded that the propagation delay time tpd be shortened while setup time and hold time, which determine the skew between an input signal and a clock signal, can be optimally adjusted.
Particularly when the employed transmission method is such that a clock signal is embedded in a serial data signal, the active edge of a clock generated by a clock recovery circuit coincides in time with a data signal change point. It is therefore important that mainly the setup time be secured. The reason is that if an attempt is made to secure a long setup time by adjusting the phase of the clock recovery circuit, the hold time, which is difficult to control, cannot be sufficiently secured due to the active edge of the next clock.
A technology for increasing the operating speed of the FF circuit is described, for instance, in Japanese Unexamined Patent Publication No. 2001-237675. A D-FF circuit described in Japanese Unexamined Patent Publication No. 2001-237675 is a master-slave D-FF circuit. This circuit can retard the operation stop clock of a master FF and advance the operation start clock of a slave FF to shorten the setup time while maintaining the propagation delay time tpd.
FIG. 1 is a diagram illustrating the configuration of the D-FF circuit described in Japanese Unexamined Patent Publication No. 2001-237675. Referring to FIG. 1, the D-FF circuit described in Japanese Unexamined Patent Publication No. 2001-237675 includes a master FF 100, an input control switch G1 for controlling the input of data DATA into the master FF 100, an input control switch G3 for controlling the input of data output from the master FF 100 into a slave FF 200, and a slave FF 200. The master FF 100 includes a feedback control switch G2 for latching input data DATA. The slave FF 200 includes a feedback control switch G4 for latching input data.
The input control switch G1 and the feedback control switch G2 operate in synchronism with control clocks CLK2, /CLK2. The input control switch G3 and the feedback control switch G4 operate in synchronism with control clocks CLK, /CLK1. A clock generator circuit 300 shown in FIG. 2 generates the control clocks CLK, /CLK1, CLK2, /CLK2 from a clock CLK.
Referring to FIG. 2, the clock generator circuit 300 (switch control circuit) includes an inverter 301, a buffer 302, and an inverter 303, which are cascade-coupled and arranged in the order named from the input side. The clock CLK is output as the clock /CLK1 through the inverter 301. The clock /CLK1 is output as the clock /CLK2 through the buffer 302. The clock /CLK2 is output as the clock CLK2 through the inverter 303. In other words, the clocks CLK2, /CLK2 are generated by retarding the clocks CLK, /CLK1.
The input control switch G1 for transmitting an input signal to the master FF 100 and the feedback control switch G2 for the master FF 100 start operating and stop in synchronism with the clocks CLK2, /CLK2 whose timings are retarded from the timing of the input control switch G3, which transmits an input signal to the slave FF 200. Therefore, the timing at which data (internal data) is loaded from the master FF 100 into the slave FF 200 is retarded. Consequently, the setup time is shorter than for the D-FF circuit, which controls the master FF and slave FF with the clock CLK alone. Meanwhile, the propagation delay time tpd is determined in accordance with the through operation start time of the slave FF 200, which operates in accordance with the clock CLK. Therefore, the setup time is shortened without changing the propagation delay time tpd. Hence, the D-FF circuit described in Japanese Unexamined Patent Publication No. 2001-237675 can shorten the setup time while maintaining the propagation delay time tpd.